As the semiconductor industry continues to scale down semiconductor devices beyond 5 nm, semiconductor nanowires are being integrated as device channels to improve performance. In vertical FETs with nanowires, it is critical to at least maintain, and preferably increase, strain to enhance performance. Stress-liner induced strain has been employed for fin-type FETs (FinFETs), but device performance from stress-liner induced strain is diminishing with contacted gate pitch (CGP) scaling and the use of replacement metal gate (RMG) in FinFETs. However, CGP scaling is relaxed in a vertical device.
A need therefore exists for a methodology to introduce stress-liner induced strain for vertical FETs and the resulting device.